In a so-called direct sequence spread spectrum communication system wherein a signal obtained by multiplying an information signal by a broadband spread code is transmitted and a received signal is returned to a narrow-band signal by reversely spreading the received signal, an information signal can be detected even under a bad C/N (carrier to noise) ratio condition of a received electric wave, so that the spread spectrum-direct communication system is promising for a code division multiple access (CDMA) which is one of multiple access methods for a mobile communications system, and for this reason, less power consumption for the device is desired.
It is known that the digital matched filter can be used for high-speed synchronized capture and synchronized tracking for extracting synchronous timing as well as for data demodulation using the extracted synchronous timing by using the output of a spread code circuit (chip: each spread code circuit constituting a spread code array is described as a "chip"), in which the advantage of the digital matched filter as a passive correlator is made use of, each time a received signal is outputted. It is also known that, even in a case where receiver timing is displaced by a period of time shorter than one spread code time, sampling by an analog/digital converter (described as "A/D converter" hereinafter) is executed at a timing of 1/2, 1/4, 1/8, 1/16 or the like of one spread code time and the digital matched filter can be used for synchronized capture, synchronized tracking, and data demodulation each with high precision by obtaining correlation output for each 1/2, 1/4, 1/8, 1/16 or the like of one spread code time.
As an example of a configuration of the passive correlator, description is made herein of a BPSK (Binary Phase Shift Keying)-accommodating matched filter, which is the most simple configuration, with reference to FIG. 10. In a receiver for spread spectrum signals, a frequency of a received signal is converted and is lowered to a frequency of a baseband signal. This signal is held as a sample and is inputted to the matched filter as an input signal. The input signal is serially inputted to a delay line 1, then signals for each delay time are outputted in parallel. This parallel output is weighted according to an output for each delay time in each tap 2. All of the weighted parallel outputs are summed in the adding circuit 3 and outputted as correlation output (correlation value).
Next description is made for operations of a digital matched filter as one of examples in which the matched filter is digitally realized with reference to FIG. 11. Block configuration similar to that in FIG. 11 is disclosed, for instance, in Japanese Patent Laid-Open Publication No. HEI 7-58669. A received spread spectrum signal generated by the receiver, which is a received baseband signal, is sampled according to timing provided from a timing signal generating circuit 5 and is converted to a digital signal by an A/D converter 4. This digital signal is successively inputted to a shift register 31. On the other hand, a spread code as reference data is generated in a spread code generating circuit 7 and is inputted once in a load-queue buffer 8 and then inputted into a buffer 30 for multiplication. Herein the load-queue buffer 8 is applied to the spread spectrum system for subjecting the digital signal to spreading by using "long spread code" having a length sufficiently longer than that of one symbol for data in addition to "short spread code" having substantially the same length as that of one symbol for information used in a normal way of spreading, and is used for temporarily accumulating therein the spread code array outputted from the spread code generating circuit 7. Accordingly, the load-queue buffer 8 is not particularly needed in a system not using the "long spread code" therefor. Data for parallel output from the shift register 31 is multiplied by data for parallel output from the buffer 30 in the multiplying circuit 12. Each result of the multiplication is summed in the adding circuit 10, and the summed data is outputted as correlation output and used for synchronized capture, synchronzed tracking, and data demodulation. In the description above, specific comment was not made for the number of bits for the A/D converter 4, but an A/D converter with a plurality of bits is generally employed for reducing quantization errors as well as for enhancing performance thereof (processing for determination using a plurality of bits is generally called soft decision processing, and processing for determination using one bit is called hard decision processing). For this reason, the shift register 31 is also required to have such configuration that the plurality of bits can be accumulated therein.
FIG. 12 is an explanatory view for explanation of a relation between an information signal and a spread code. An information signal comprises a plurality of information bits each of which is a basic unit thereof. In an example 1 of spread code, one information bit length is spread by five spread code bits of 00110. The spread code length in this case is expressed as follows: Spread code length=5. On the other hand, in an example 2 of spread codes, a two-information bit is spread by 10 spread code bits of 0011010011. The spread code length in this case is expressed as follows: Spread code length=10. However, it is found that one information bit in the above case is also spread by five spread code bits. Also a period of time required for multiplying an information signal by one spread code is expressed as one spread code time. The examples 1, 2 of spread codes show examples each indicating one spread code time identical to each other respectively.
A digital matched filter based on the conventional technology has the configuration in which a received signal obtained by sampling is accumulated in a shift register and the received signal is shifted each time sampling. Especially, in a case where the A/D converter with a plurality of bits is used for enhancing the capability, the shift register is also required to accumulate therein and further shift the plurality of bits. In a digital circuit, a potential in the circuit generally fluctuates when a signal is changed, and power is consumed (it is known to require power consumption when binary numerals 0, 1 of an output signal are changed especially for a device such as a CMOS using process). Accordingly, power consumption is largely required also for a plurality of bits-accommodating shift register when data is shifted.